1. Field of the Invention
This invention generally relates to the formation of openings through a dielectric layer during the fabrication of an integrated circuit, and more particularly to a technique of etching passages with sloped sidewalls through the dielectric layer to expose contacts in an internal layer below the dielectric layer, particularly during the formation of conductive contact holes.
2. Description of the Prior Art
The fabrication of integrated circuits often requires the creation of interconnections between layers, conventionally accomplished by creating electrically conducting passageways or connections through contact holes or vias. Contact holes are conventionally fabricated by placing contacts on an internal layer, including the silicon substrate, covering such internal layer and contacts with an insulating or dielectric layer, etching passages through the dielectric layer to expose the contacts and metalizing the passages to provide electrically conducting paths to the contacts.
Several problems exist with the conventional techniques used for forming such inter layer interconnections, and in particular, with the techniques used for etching the required passages, or passageways. A simplified description of the conventional approach for forming contact holes through a dielectric layer for interconnection to contacts on the surface of a substrate will be described next.
In the formation of such conventional contact holes, the deposition of the dielectric layer normally forms a layer of equal thickness over the surface of the substrate and the contacts. Those contacts having profiles raised above the surface of the substrate create high spots in the top surface of dielectric layer as shown, for example, by high spots 11, 13, and 15 in FIG. 1.
Before the appropriate passages are etched, it is often necessary to planarize the dielectric layer, i.e., to remove elevated areas such as high spots 11, 13, and 15. One common approach to planarizing the dielectric layer is to spin a planar coat of photoresist over the surface of the layer. The photoresist and the high spots of the dielectric layer are then removed together during a reactive ion etch.
The photoresist material utilized is selected to be etchable at the same rate as the dielectric. This permits the planar surface of the photoresist layer to be maintained as the etch removes the high spots of the dielectric. The etch is stopped after all the photoresist has been eroded away and the surface of the dielectric is planar.
Thereafter, to form the passages, another layer of photosensitive, patternable photoresist is applied over the planarized dielectric layer. The photoresist is exposed with a mask related to the contacts, developed and either the exposed, or the unexposed, photoresist is removed. The resulting photoresist pattern exposes the dielectric above the contacts.
An etching process is then used to form passages through the dielectric layer exposing the contacts. Metal is then deposited in the passages in electrical contact with the contacts on the substrate to form the desired electrical connections.
The etching of the patterned photoresist and the dielectric layer is controlled to form the passages with a predetermined sidewall configuration in the same general manner as shown, for example, by sloped sidewall portion 29 and vertical sidewall portion 27 in FIG. 5. This combination of sloped and vertical sidewalls has been found to be beneficial during the subsequent metal deposition step.
There are several problems associated with such conventional techniques. In general, the planarization required to compensate for contacts having differing raised profiles makes it difficult to consistently etch the passages with properly configured sidewalls and without harmfully affecting the contacts by over-etching.
In particular, after conventional planarization, the dielectric layer will be of differing thicknesses over contacts of differing profile heights above the substrate. The higher profile contacts will be closer to the surface of the dielectric. During etching, contacts closest to the surface are exposed first. As the etching process is continued to expose the remaining contacts, the first exposed contacts may become over-etched, resulting in high contact resistance.
Another problem with the current techniques is the over-etching of passage sidewalls. The over-etching of sidewalls may cause the loss of desired sidewall configuration. The conventionally desired sidewall configuration includes a vertical sidewall near the contact and a sloped sidewall outward therefrom to the dielectric surface, in the general shape of an inverted funnel or frustum, as discussed above with reference to FIG. 5. Overetching can cause the loss of the vertical portion of the sidewall.
With contacts of varying profile heights, the use of the conventional techniques are limited because it is difficult to control over-etching of the shallower contacts, and/or verticality of the sidewalls near these contacts. These restrictions mandate very narrow manufacturing process margins. As a result, the conventional techniques are relatively expensive and have limited application.
What is needed is a technique which reliably and inexpensively forms contact holes on planarized dielectric with properly configured passageways through the dielectric layer to contacts of varying profile heights on the substrate or other internal layer.